1. Field of the Invention
The present invention relates to an image processing apparatus for processing image data taken by an imaging device and a method for controlling such an image processing apparatus.
2. Description of the Related Art
Some solid-state imaging devices proposed in recent years are designed to output data constituting a plurality of pixels in serial form, in such a manner that the pixels were output individually and in parallel. Such imaging devices are disclosed illustratively by Japanese Patent Laid-Open Nos. 2005-86224 and 2005-244709. These solid-state imaging devices make it easy to change the number of parallelly output pixels. Illustratively, the number of pixels output in parallel by the device is readily changed in accordance with the frame rate or the pixel count in effect.
Image processing apparatuses for processing the image data output by the above-cited type of solid-state imaging device typically keep their power dissipation in check by reducing their clock frequencies or by lowering their source voltages. However, such arrangements are becoming insufficient in bringing down power consumption. The reason is that in the face of advances in fine pattern lithography for processing semiconductors, leak currents are on the increase and source voltages have little room for further reductions.
There are lower limits to the operating frequencies of some memory units such as DDR2-SDRAMs (double-data-rate2 synchronous dynamic random access memory). Even if there is a surplus bandwidth capacity for access to this type of memory unit, it is impossible to bring its operating frequency under a given lower frequency limit. This makes it difficult to keep the power dissipation of the memory units low enough.
Japanese Patent Laid-Open No. 2002-259327 discloses a bus control apparatus for changing the width of a bus from one setting to another in keeping with the data traffic being monitored on that bus. One disadvantage of the disclosed apparatus is that it needs a traffic monitoring device when configured. Another disadvantage is that delays in bus width changeover are bound to occur because the process of data traffic monitoring precedes the operation of bus width changeover in the apparatus. The latter disadvantage in particular makes it difficult for the cited bus control apparatus to keep up with rapid ups and downs in data traffic.
Japanese Patent Laid-Open Nos. 2006-313645 and Sho 58-122688 disclose techniques for changing the number of data lines on memory units by changing the connective relations between the data lines and memory arrays. These techniques are for changing the mapping of the memory arrays in use. That is, reductions in data width are matched by increases in the number of words. Moreover, the disclosed techniques are irrelevant to stopping the clock feed to part of the memory arrays or partially halting power supply to the memory arrays.
Furthermore, the proposed techniques above for changing memory array mapping are not shown applicable to inexpensive, common memory units such as SDRAMs (synchronous dynamic random access memory), DDR-SDRAMs (double-data-rate synchronous dynamic random access memory) and DDR2-SDRAMs. In other words, these techniques are not available on the cheap.